1. Field of the Invention
The present invention relates to a method of manufacturing monolithic integrated circuits and more particularly to a method for forming electronic components of two different types each having pairs of electrodes separated by different dielectric materials on a substrate of a semiconductor material.
2. Description of the Prior Art
Integrated circuits, called microprocessors or microcontrollers, are known which form complex circuit systems generally comprising a memory unit, a processing unit and input and output interface circuits.
The memory units comprise matrices of random access memory (RAM) cells, matrices of non-volatile fixed program memory (ROM) cells and matrices of non-volatile electrically programmable memory (EPROM and/or EEPROM) cells having two levels of polycrystalline silicon. The processing unit and, in particular, the interface circuits require a large number of capacitors for their operation.
The EPROM and EEPROM memory cells and the capacitors have a structure which is similar in certain respects, since they both have two electrodes separated by a dielectric, as a result of which some of the stages of manufacture of these two types of components may in principle be common.
However, the functional characteristics of the memory cells and capacitors are, as is known, very different and if the same manufacturing stages are to be used for both it is necessary to use compromise solutions which do not make it possible to obtain the structures which are most advantageous for the correct operation and maximum integration density for either the memory cells or the capacitors.
A conventional technique for the manufacture of integrated circuits of this type comprises the deposition of a first layer of polycrystalline silicon to form the "floating" gate electrode of the memory cells and a first electrode of the capacitors, the formation of a layer of silicon dioxide by growth at a high temperature so as to form the so-called "interpoly" dielectric of the memory cells and the dielectric of the capacitors and then the deposition of a second layer of polycrystalline silicon to form the control electrode of the cells and the second electrode of the capacitors.
Although this technique is very advantageous from the economic point of view, since the memory cells and capacitors are obtained by the same method steps, it is not convenient in many cases since if the method is developed to provide high quality cells, it is impossible to choose the most appropriate specific capacitance or the best dielectric for the capacitors since the thickness and physical characteristics of the dielectric are determined by the desired cell structure. Furthermore, as it is necessary to keep the level of doping of the first polycrystalline silicon layer low (resistivity greater than 200 ohm/square cm) to obtain a high quality "interpoly" dielectric for the correct operation of the memory cells, it is not possible to obtain capacitors having a sufficiently low voltage coefficient (the voltage coefficient is the percentage variation of the capacitance as a function of the voltage applied to the electrodes of the capacitor). The values which can be obtained with this method are not less than 300 ppm/Volt, while the values required for a high quality capacitor are less than 20 ppm/Volt.
One way of partially remedying the drawbacks of the prior art would be to increase the doping of the polycrystalline silicon solely in the capacitor zones, by suitable masking and implantation operations thereon. In this way the capacitors would have fairly low voltage coefficients, but would nevertheless be subject to the constraints imposed by the thickness and physical characteristics of the dielectric desired for the memory cells. Moreover, as a result of the formation of the silicon dioxide by growth, the dimensioning of the capacitors would be rather critical since it would be conditioned by a method parameter which is difficult to control, i.e. the doping of the first polycrystalline silicon layer. As is known, the rate of growth of the oxide depends on the doping of the underlying silicon.
According to a further known method, a third level of polycrystalline silicon is used for the integration of capacitors and memory cells having two levels of polycrystalline silicon without the drawbacks of the prior art.
It is possible in this way to construct the electrodes of the cells and capacitors separately, but with the addition of manufacturing stages which are often critical from the point of view of the quality of the finished components. In particular, there are problems with the complete removal of the portions of the third polycrystalline silicon layer from the zones of the memory cells where there are substantial reliefs and depressions, and there is a detrimental effect on the planar nature of the final surface of the integrated circuit, particularly in those zones in which the three layers of polycrystalline silicon are superimposed in contact with one another, which, as is known, compromises the good quality and reliability of the metal connections between the components of the integrated circuit.